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INTEGRATED CIRCUITS
DATA SHEET
PCF2113x LCD controller/driver
Product specification Supersedes data of 1996 Oct 21 File under Integrated Circuits, IC12 1997 Apr 04
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 9 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.6.3 9.7 9.8 9.9 9.10 9.11 10 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS FUNCTIONAL DESCRIPTION LCD supply voltage generator Programming ranges LCD bias voltage generator Oscillator External clock Power-on reset Power-down mode Registers Busy Flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Reset function INSTRUCTIONS Clear display Return home Entry mode set I/D S Display control (and partial power-down mode) D C B Cursor/display shift Function set DL (parallel mode only) M H Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES 2
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 11 12 12.1 12.2 12.3 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 21.1 21.2 21.3 21.4 22 23 24
New instructions Icon control IM IB Normal/Icon mode operation Screen configuration Display configuration TC1, TC2 Set VLCD Reducing current consumption INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics of the I2C-bus I2C-bus protocol Definitions LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION 8-bit operation, 1-line display using internal reset 4-bit operation, 1-line display using internal reset 8-bit operation, 2-line display I2C operation, 1-line display BONDING PAD LOCATIONS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Apr 04
Philips Semiconductors
Product specification
LCD controller/driver
1 FEATURES
PCF2113x
* MUX rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode) * Uses common 11 code instruction set (extended) * Logic supply voltage range, VDD - VSS = 1.8 to 4.0 V (up to 5.5 V if external VLCD is used); chip may be driven with two battery cells * Display supply voltage range, VLCD - VSS = 2.2 to 6.5 V * Very low current consumption (20 to 200 A): - icon mode: <25 A - power-down mode: <2.5 A. 2 APPLICATIONS
* Single-chip LCD controller/driver * 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user defined symbols * Icon mode: reduced current consumption while displaying icons only(1) * Icon blink function * On-chip: - generation of LCD supply voltage, programmable by instruction (external supply also possible) - temperature compensation of on-chip generated VLCD: -8 to -12 mV/K at 5.0 V (programmable by instruction) - generation of intermediate LCD bias voltages - oscillator requires no external components (external clock also possible) * Display data RAM: 80 characters * Character generator ROM: 240, 5 x 8 characters * Character generator RAM: 16, 5 x 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon-blink feature is used in application * 4 or 8-bit parallel bus and 2-wire I2C-bus interface * CMOS compatible * 18 row, 60 column outputs
(1) Icon mode is used to save current. When only icons
* Telecom equipment * Portable instruments * Point-of-sale terminals. 3 GENERAL DESCRIPTION
are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. Never use the voltage generator in icon mode. 4 ORDERING INFORMATION
The PCF2113x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 line by 12 and 1 line by 24 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. Three character sets (A, D and E) are currently available (see Figs 7, 8 and 9). Various other character sets can be manufactured on request.
PACKAGE TYPE NUMBER NAME PCF2113AU/10/F2 PCF2113DU/10/F2 PCF2113DU/F2 PCF2113DH/F2 PCF2113EU/2/F2 - - - LQFP100 - DESCRIPTION chip on flexible film carrier chip on flexible film carrier chip in tray plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm chip with bumps in tray VERSION - - - SOT407-1 -
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
5 BLOCK DIAGRAM
PCF2113x
handbook, full pagewidth
C1 to C60 18 to 77 60
R1 to R18 9 to 17 78 to 86
18
8 VLCD1
BIAS VOLTAGE GENERATOR
COLUMN DRIVERS 60 DATA LATCHES
ROW DRIVERS 18 SHIFT REGISTER 18-BIT
7 VLCD2
VLCD GENERATOR
60 SHIFT REGISTER 5 x 12 BIT 5 CURSOR AND DATA CONTROL 5 2 OSC
OSCILLATOR
VDD1, 2
1, 100
5, 6 VSS1, 2
CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS 8
CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
TIMING GENERATOR
T1
4 7
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
3
PD
PCF2113x
DATA REGISTER (DR) 8 I/O BUFFER 96 to 99 DB0 to DB3/SA0 92 to 95 E 89 91 90 RS 87 SCL 88
MGE990
8 BUSY FLAG INSTRUCTION REGISTER 8 POWER-ON RESET
DB4 to DB7
R/W
SDA
Fig.1 Block diagram.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
6 PINNING SYMBOL VDD1 OSC PD T1 VSS1 VSS2 VLCD2 VLCD1 R9 to R16 R18 C60 to C1 R8 to R1 R17 SCL SDA E RS R/W DB7 DB6 DB5 DB4 DB3/SA0 DB2 DB1 DB0 VDD2 Notes PIN 1 2 3 4 5 6 7 8 9 to 16 17 18 to 77 78 to 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TYPE P I I I P P O I O O O O O I I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O P DESCRIPTION supply voltage for all except high voltage generator oscillator/external clock input power-down pad input test pad (connected to VSS) ground for all except high voltage generator ground for high voltage generator VLCD output; note 1 VLCD input; note 2 LCD row driver outputs 9 to 16 LCD row driver output 18 LCD column driver outputs 60 to 1 LCD row driver outputs 8 to 1 LCD row driver output 17 I2C serial clock input I2C serial data input/output data bus clock input register select input read/write input 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bi-directional data bus/I2C address pin 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bidirectional data bus 1 bit of 8-bit bidirectional data bus supply voltage for high voltage generator; note 3
PCF2113x
1. This is the VLCD output pin, if VLCD is generated internally and has to be connected to VLCD1. If VLCD1 is generated externally, VLCD2 has to be left open or connected to ground. 2. This is the voltage used for the generation of LCD bias levels. 3. This is the supply for the high voltage generator. If VLCD is generated externally, connect VDD2 to VSS.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth
100 VDD2
96 DB3/SA0
88 SDA
99 DB0
98 DB1
97 DB2
95 DB4
94 DB5
93 DB6
92 DB7
87 SCL
91 R/W
86 R17
90 RS
85 R1
84 R2
83 R3
82 R4
81 R5
80 R6
79 R7
78 R8
77 C1
VDD1 OSC PD T1 VSS1 VSS2 VLCD2 VLCD1 R9
1 2 3 4 5 6 7 8 9
76 C2 75 C3 74 C4 73 C5 72 C6 71 C7 70 C8 69 C9 68 C10 67 C11 66 C12 65 C13 64 C14 63 C15 62 C16 61 C17 60 C18 59 C19 58 C20 57 C21 56 C22 55 C23 54 C24 53 C25 52 C26 51 C27 C28 50
R10 10 R11 11 R12 12 R13 13 R14 14 R15 15 R16 16 R18 17 C60 18 C59 19 C58 20 C57 21 C56 22 C55 23 C54 24 C53 25 C52 26 C51 27 C50 28 C49 29 C48 30 C47 31 C46 32 C45 33 C44 34 C43 35 C42 36 C41 37 C40 38 C39 39 C38 40 C37 41 C36 42 C35 43 C34 44 C33 45 C32 46 C31 47 C30 48 C29 49
PCF2113x
89 E
MGE989
Fig.2 Pin configuration (LQFP100).
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
7 PIN FUNCTIONS NAME RS FUNCTION register select DESCRIPTION
PCF2113x
RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. There is an internal pull-up on this pin. RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read. RS = logic 1 selects the data register for both read and write.
R/W
read/write
R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when the device is controlled by the parallel interface. There is an internal pull-up on this pin. The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when I2C-bus control is used. The parallel interface of the device. This bi-directional, 3-state data bus transfers data between the system controller and the PCF2113x. There is an internal pull-up on each of the data lines. DB7 to DB0 must be connected to VDD or left open circuit when I2C-bus control is used. Note that DB3 shares the same pin as SA0. In 4-bit operations only DB7 to DB4 are used, and DB3 to DB0 must be left open circuit. See note 1. DB7 may be used as the Busy Flag, signalling that internal operations are not yet completed.
E
data bus clock
DB7 to DB0 data bus
C1 to C60 R1 to R18 VLCD OSC SCL SDA SA0
column driver outputs row driver outputs LCD power supply oscillator serial clock line serial data line address pin
These pins output the data for columns. These pins output the row select waveforms to the display. R17 and R18 drive the icons. Positive power supply for the liquid crystal display. This may be generated on-chip or supplied externally. When the on-chip oscillator is used this pin must be connected to VDD. An external clock signal, if used, is input at this pin. Input for the I2C-bus clock signal. SCL must be connected to VSS or VDD when the parallel interface is used. I/O for the I2C-bus data line. SDA must be connected to VSS or VDD when the parallel interface is used. The hardware sub-address line is used to program the device sub-address for two different PCF2113xs on the same I2C bus. Note that SA0 shares the same pin as DB3. T1 must be connected to VSS and is not user accessible.
T1 PD Note
test pad
power-down pad PD selects chip power-down mode. For normal operation PD = logic 0.
1. If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
8 8.1 FUNCTIONAL DESCRIPTION (see Fig.1) LCD supply voltage generator
PCF2113x
Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. VB must be programmed to FF in character mode and VA must be programmed to 00 in icon mode. When VLCD is generated on-chip the VLCD pins should be decoupled to VSS with a suitable capacitor. The generated VLCD is independent of VDD and is temperature compensated. When the generator is switched off an external voltage may be supplied at connected pins VLCD1,2. VLCD1,2 may be higher or lower than VDD if external VLCD is used. If internally generated it must not be lower than VDD and V DD 4V . 8.3 LCD bias voltage generator
The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit registers, VA and VB. The nominal LCD operating voltage at room temperature is given by the relationships: VOP(nom) = [(integer value of register) x 0.08 + 1.9] V 8.2 Programming ranges (Tref = 27 C)
Programmed value range: 1 to 63. Voltage range: 1.90 to 6.84 V. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD temperature coefficient must be taken into account. Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Value 0 for VA and VB switches the generator off.
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given in Tables 1 and 2. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids.
Table 1
Optimum/maximum values for VOP (off pixels start darkening; Voff = Vth) NUMBER OF LEVELS 5 3 Von/Vth 1.272 2.236 VOP/Vth 3.7 2.283 VOP (typical; for Vth = 1.4 V) 5.2 V 3.9 V
MUX RATE 1 : 18 1:2 Table 2
Minimum values for VOP (on pixels clearly visible; Von > Vth) NUMBER OF LEVELS 5 3 Von/Vth 1.12 1.2 VOP/Vth 3.2 1.5 VOP (typical; for Vth = 1.4 V) 4.6 V 2.1 V
MUX RATE 1 : 18 1:2 8.4 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD. 8.5 External clock
Only in the power-down state is the clock allowed to be stopped (OSC connected to Vss), otherwise the LCD is frozen in a DC state. 8.6 Power-on reset
If an external clock is to be used this is input at the OSC pin. The resulting display frame frequency is given by f OSC f frame = ------------3 072
The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 OSC cycles to be executed.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
8.7 Power-down mode 8.11 Display Data RAM (DDRAM)
PCF2113x
The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all LCD-outputs are internally connected to VSS) when PD = logic 1. During power-down, the whole chip is reset and will restart with a clear display after power-down. Therefore, the whole chip has to be initialized after a power-down as after initial power- up. The device should be put into `display off' mode (instruction `Display control') before putting the chip in power-down mode, otherwise the LCD output voltages are not defined. 8.8 Registers
The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00 in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap- around operations for the various modes are shown in Table 3. Table 3 Address space and wrap-around operation MODE address space read/write wrap-around (moves to next line) 1 x 24 2 x 12
The PCF2113x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as `Display clear' and `Cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written from but not read by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `Read data' instruction. 8.9 Busy Flag
00 to 4F 00 to 27; 40 to 67 4F to 00 27 to 40; 67 to 00
display shift wrap-around 4F to 00 27 to 00; 67 to 40 (stays within line) 8.12 Character Generator ROM (CGROM)
The Busy Flag indicates the free/busy status of the PCF2113x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic 0 and R/W = logic 1. Instructions should only be written after checking that the Busy Flag is logic 0 or waiting for the required number of cycles. 8.10 Address Counter (AC)
The Character Generator ROM (CGROM) generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figures 7, 8 and 9 show the character sets that are currently implemented. 8.13 Character Generator RAM (CGRAM)
The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions `Set CGRAM address' and `Set DDRAM address'. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB6 to DB0) when RS = logic 0 and R/W = logic 1.
Up to 16 user defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 10 shows the addressing principle for the CGRAM.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
8.14 Cursor control circuit 8.16 LCD row and column drivers
PCF2113x
The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.6) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited. 8.15 Timing generator
The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 11, 12 and 13 show typical waveforms. Unused outputs should be left unconnected.
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.
handbook, full pagewidth
display position DDRAM address
non-displayed DDRAM addresses 12345
00 01 02 03 04
22 23 24
15 16 17 18 19 4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345
00 01 02 03 04
10 11 12
09 0A 0B 0C 0D 24 25 26 27
line 1
DDRAM address
12345
40 41 42 43 44
10 11 12
49 4A 4B 4C 4D 64 65 66 67
MGE991
line 2
2-line display
Fig.3 DDRAM-to-display mapping: no shift.
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
14 15 16
4F 00 01 02 03
1-line display 1 DDRAM address 23 4 5 10 11 12
08 09 0A
27 00 01 02 03
line 1
1
23
4
5
10 11 12
48 49 4A
MGE992
67 40 41 42 43
line 2
2-line display
Fig.4 DDRAM-to-display mapping: right shift.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
16 17 18
01 02 03 04 05
1-line display 1 DDRAM address 23 4 5 10 11 12
0A 0B 0C
01 02 03 04 05
line 1
1
23
4
5
10 11 12
4A 4B 4C
MGE993
41 42 43 44 45
line 2
2-line display
Fig.5 DDRAM-to-display mapping: left shift.
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.6 Cursor and blink display examples.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGE994
Fig.7 Character set `A' in CGROM: PCF2113A.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGD688
Fig.8 Character set `D' in CGROM: PCF2113D.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGD689
Fig.9 Character set `E' in CGROM: PCF2113E.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
character handbook, full pagewidth codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
MGE995
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' instruction. Bit 6 can be set using the `set DDRAM address' instruction in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction.
Fig.10 Relationship between CGRAM addresses and data and display patterns.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 9
ROW 2
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
MGE996
123
18 1 2 3
18
Fig.11 Typical LCD waveforms; character mode.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth
frame n
frame n + 1 only icons are driven (MUX 1 : 2)
VLCD ROW 17 2/3 1/3 VSS
VLCD ROW 18 2/3 1/3 VSS
VLCD ROW 1 to 16 2/3 1/3 VSS
VLCD COL 1 ON/OFF 2/3 1/3 VSS
VLCD COL 2 OFF/ON 2/3 1/3 VSS
VLCD COL 3 ON/ON 2/3 1/3 VSS
VLCD COL 4 OFF/OFF 2/3 1/3 VSS
MGE997
Fig.12 MUX 1 : 2 LCD waveforms; icon-mode.
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Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth V PIXEL
frame n
frame n + 1 state 1 (ON)
state 1 COL 1 ROW 17
VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP
state 2 (OFF)
R17 R18 R1-16
state 3 (OFF)
state 2 COL 2 ROW 17
state 3 COL 1 0 ROW 1 to 16 -1/3 VOP -2/3 VOP -VOP
MGE998
VON(rms) = 0.745VOP. VOFF(rms) = 0.333VOP. V ON D = ------------- = 2.23 V OFF
Fig.13 MUX 1 : 2 LCD waveforms; icon-mode.
1997 Apr 04
18
Philips Semiconductors
Product specification
LCD controller/driver
8.17 Reset function
PCF2113x
The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, requiring 165 OSC cycles. After the reset the chip's functions are in the states shown in Table 4. Table 4 STEP 1 2 3 State after reset FUNCTION clear display entry mode set display control I/D = 1 S=0 D=0 C=0 B=0 4 function set DL = 1 M=0 H=0 5 6 7 8 9 10 +1 (increment) no shift display off cursor off cursor character blink off 8-bit interface 1-line display normal instruction set RESET STATE (BIT/REGISTER) RESET STATE (DESCRIPTION)
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = logic 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 17 and 18 icon control display/screen configuration VLCD temperature coefficient set VLCD I2C-bus interface reset IM, IB = 00 L, P, Q = 000 TC1, TC2 = 00 VA, VB = 0 icons/icon blink disabled default configurations default temperature coefficient VLCD generator off
1997 Apr 04
19
Philips Semiconductors
Product specification
LCD controller/driver
9 INSTRUCTIONS
PCF2113x
In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instruction other than the `Read busy flag and address' instruction will be executed. Because the Busy Flag is set to logic 1 while an instruction is being executed, check to make sure it is on logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 6. An instruction sent while the Busy Flag is logic 1 will not be executed.
Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers, to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The format for instructions when I2C-bus control is used is shown in Table 5. The PCF2113x operation is controlled by the instructions shown in Table 6, which also gives execution times in clock cycles. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2113x functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. Table 5 Instruction format for I2C-bus instructions CONTROL BYTE(1) Co Note 1. R/W is set together with the slave address. RS 0 0 0 0 0 0
COMMAND BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
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1997 Apr 04 21
Philips Semiconductors
Table 6
Instructions
LCD controller/driver
INSTRUCTION H = 0 or 1 NOP Function set
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED CLOCK CYCLES
0 0
0 0
0 0
0 0
0 1
0 DL
0 0
0 M
0 0
0 H
no operation sets interface Data Length (DL) and number of display lines (M); extended instruction set control (H) reads the Busy Flag (BF) indicating internal operating is being performed and reads Address Counter contents reads data from CGRAM or DDRAM writes data from CGRAM or DDRAM
3 3
Read busy flag and address Read data Write data H=0 Clear display Return home
0
1
BF
AC
0
1 1
1 0
read data write data
3 3
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
clears entire display and sets DDRAM address 0 in Address Counter sets DDRAM address 0 in Address Counter; also returns shifted display to original position; DDRAM contents remain unchanged sets cursor move direction and specifies shift of display; these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into power-down mode moves cursor and shifts display without changing DDRAM contents sets CGRAM address; bit 6 is to be set by the instruction `Set DDRAM address'; look at the description of the instructions sets DDRAM address
165 3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift Set CGRAM address Set DDRAM address
0 0
0 0
0 0
0 1
0
1
S/C
R/L
0
0
3 3 Product specification
ACG
PCF2113x
0
0
1
ADD
3
1997 Apr 04 22
Philips Semiconductors
INSTRUCTION H=1 Reserved Screen configuration Display configuration Icon control Temperature control Reserved Set VLCD Note 1. X = don't care.
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED CLOCK CYCLES - 3 3 3 3 - 3
LCD controller/driver
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 V
0 0 0 0 0 X(1)
0 0 0 0 1 X(1)
0 0 0 1 0 X(1)
0 0 1 IM 0 X(1)
0 1 P IB
1 L Q 0
do not use set screen configuration set display configuration set icon mode (IM), icon blink (IB)
TC1 TC2 set temperature coefficient (TCx) X(1) X(1) do not use store VLCD in register VA or VB (V)
voltage
Product specification
PCF2113x
Philips Semiconductors
Product specification
LCD controller/driver
Table 7 Explanations of symbols used in Table 6 0 decrement display freeze display off cursor off cursor character blink off: character at cursor position does not blink cursor move left shift 4 bits use basic instruction set left/right screen: standard connection (as in PCF2114); 1st 12 characters of 24: columns are from 1 to 60 2nd 12 characters of 24: columns are from 1 to 60 column data: left to right (as in PCF2116); column data is displayed from 1 to 60 row data: top to bottom (as in PCF2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 character mode; full display icon blink disabled set VA 1-line by 24 display last control byte; see Table 5 Explanation of TC1 and TC2 used in Table 6 TC2 0 0 1 1 VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3; for ranges for TC see Chapter 15 DESCRIPTION increment display shift display on cursor on 1
PCF2113x
BIT I/D S D C B S/C R/L DL H L (no impact, if M = 1)
cursor character blink on: character at cursor position blinks display shift right shift 8 bits use extended instruction set left/right screen: mirrored connection (as in PCF2116); 1st 12 characters of 24: columns are from 1 to 60 2nd 12 characters of 24: columns are from 60 to 1 column data: right to left; column data is displayed from 60 to 1 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 icon mode; only icons displayed icon blink enabled set VB 2-line by 12 display another control byte follows after data/instruction
P Q
IM IB V M C0 Table 8 TC1 0 1 0 1
1997 Apr 04
23
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.14 4-bit transfer example.
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction 7th, 3rd bit. AC3: Address Counter 3rd bit. D7, D3: data 7th, 3rd bit.
Fig.15 An example of 4-bit data transfer timing sequence.
1997 Apr 04
24
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.16 Example of Busy Flag checking timing sequence.
9.1
Clear display
9.3 9.3.1
Entry mode set I/D
`Clear display' writes character code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be blank pattern), sets the DDRAM Address Counter to logic 0 and returns display to its original position if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = logic 1 (increment mode). S of entry mode does not change. The instruction `Clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. 9.2 Return home
When I/D = logic 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 9.3.2 S
`Return home' sets the DDRAM Address Counter to logic 0 and returns display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.
When S = logic 1, the entire display shifts either to the right (I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM write. Thus it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing into or reading out of the CGRAM. When S = logic 0 the display does not shift.
1997 Apr 04
25
Philips Semiconductors
Product specification
LCD controller/driver
9.4 9.4.1 Display control (and partial power-down mode) D
PCF2113x
The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor shift'. 9.6 9.6.1 Function set DL (PARALLEL MODE ONLY)
The display is on when D = logic 1 and off when D = logic 0. Display data in the DDRAM are not affected and can be displayed immediately by setting D to logic 1. When the display is off (D = logic 0) the chip is in partial power-down mode: * The LCD-outputs are connected to VSS * The LCD generator and bias generator are turned off. 3 OSC cycles are required after sending the `Display off' instruction to ensure all outputs are at VSS, afterwards OSC can be stopped. If the oscillator is running during partial power-down mode (`Display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS). To ensure IDD < 1 A the parallel bus pins DB7 to DB0 should be connected to VDD; RS, R/W, to VDD or left open and PD to VDD. Recovery from power-down mode: PD back to logic 0, if necessary OSC back to VDD, send a `Display control' instruction with D = logic 1. 9.4.2 C
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = logic 1 or in two nibbles (DB7 to DB4) when DL = logic 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open (internal pull-ups). Hence in the first `Function set' instruction after power-on N and H are set to logic 1. A second `Function set' must then be sent (2 nibbles) to set N and H to their required values. `Function set' from I2C-interface sets the DL bit to logic 1. 9.6.2 M
Chooses either 1-line by 24 display (M = 0) or 2-line by 12 display (M = 1). 9.6.3 H
The cursor is displayed when C = logic 1 and inhibited when C = logic 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.6). 9.4.3 B
When H = logic 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = logic 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 9.7 Set CGRAM address
The character indicated by the cursor blinks when B = logic 1. The cursor character blink is displayed by switching between display characters and all dots on with f OSC a period of approximately 1 s, with f BLINK = ---------------52 224 The cursor underline and the cursor character blink can be set to display simultaneously. 9.5 Cursor/display shift
`Set CGRAM address' sets bits 5 to 0 of the CGRAM address (ACG in Table 6) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A[6] to A[0]). With the `Set CGRAM address' instruction, only bits 5 down to 0 are set. Bit 6 can be set using the `Set DDRAM address' instruction first, or by using the auto-increment feature during CGRAM write. All of bits 6 to 0 can be read using the `Read busy flag and address' instruction. When writing to the lower part of the CGRAM, make sure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action).
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
9.8 Set DDRAM address
PCF2113x
10 EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES 10.1 New instructions
`Set DDRAM address' sets the DDRAM address (ADD in Table 6) into the Address Counter (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. 9.9 Read busy flag and address
H = logic 1 sets the chip into alternate instruction set mode. 10.2 Icon control
`Read busy flag and address' reads the Busy Flag (BF) and Address Counter (AC). BF = logic 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction. At the same time, the value of the Address Counter expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM
The PCF2113x can drive up to 120 icons. See Fig.17 for CGRAM to icon mapping. 10.3 IM
When IM = logic 0 the chip is in character mode. In character mode characters and icons are driven (MUX 1 : 18). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = logic 1 the chip is in icon mode. In icon mode only the icons are driven (MUX 1 : 2) and the VLCD voltage generator, if used, produces the VLCD voltage programmed in register VB. Remark: If internally generated VLCD must not be lower than VDD (VDD 4 V) 10.4 IB
`Write data' writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `Set CGRAM address' or `Set DDRAM address' instruction. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are `don't care'. 9.11 Read data from CGRAM or DDRAM
Icon blink control is independent of the cursor/character blink function. When IB = logic 0 icon blink is disabled. Icon data is stored in CGRAM character 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). When IB = logic 1 icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not used. Icon states for the odd phase are stored in CGRAM character 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters.
`Read data' reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `Set address' instruction determines whether the CGRAM or DDRAM is to be read. The `Read data' instruction gates the content of the Data Register (DR) to the bus while E is high. After E goes low again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Note: the only three instructions that update the Data Register (DR) are: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `Write data', `Cursor/display shift', `Clear display', `Return home') do not modify the data register content.
1997 Apr 04
27
Philips Semiconductors
Product specification
LCD controller/driver
Table 9 Blink effect for icons and cursor character blink PARAMETER Cursor underline Cursor character blink Icons on block (all on) state 1: CGRAM character 0 to 2 EVEN PHASE off
PCF2113x
ODD PHASE normal (display character) state 2: CGRAM character 4 to 6
handbook, full pagewidth
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 -
1
2
3
4
5
6
7
8
9
10
56
57
58
59
60
ROW 18 -
61
62
63
64
65
66
67
68
69
70
116 117 118 119 120
MGE999
block of 5 columns
icon no. handbook, full pagewidth
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
56-60 61-65
even even
17/56-60 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 0
0 0
1 1
0 1
1 0
1 0
1 1
1 1
1 0
1 0
1 0
116-120 1-5
even odd (blink)
18/56-60 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
0 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
MGG001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 2 define the icon-states when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 6 define the icon-state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.17 CGRAM to icon mapping.
1997 Apr 04
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Philips Semiconductors
Product specification
LCD controller/driver
10.5 IM 0 1 10.6 Normal/Icon mode operation CONDITION character mode icon mode Screen configuration VLCD generates VA generates VB VLCD programming: 1. 2.
PCF2113x
send `Function set' instruction with H = 1 send `Set VLCD' instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) c) DB5 to DB0 = 000000 switches VLCD generator off (when selected) d) During `display off' and power-down VLCD generator is also disabled
L: default is L = logic 0. L = logic 0: the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120. L = logic 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout. 10.7 Display configuration
3. send `Function set' instruction with H = 0 to resume normal programming. 10.10 Reducing current consumption Reducing current consumption can be achieved by one of the options mentioned in Table 10. Table 10 Reducing current consumption ORIGINAL MODE Character mode Display on ALTERNATIVE MODE icon mode (control bit IM) display off (control bit D)
P, Q: default is P, Q = logic 0. P = logic 1 mirrors the column data. Q = logic 1 mirrors the row data. 10.8 TC1, TC2
Default is TC1, TC2 = logic 0. This selects the default temperature coefficient for the internally generated VLCD. TC1,TC2 = 10,01 and 11 selects alternative temperature coefficients 1, 2 and 3 respectively. 10.9 Set VLCD
VLCD value is programmed by instruction. Two on-chip registers hold VLCD values for character mode and icon mode respectively (VA and VB). The generated VLCD value is independent of VDD, allowing battery operation of the chip. VB must be programmed to FF in character mode (i.e. using VA) and VA must be programmed to 00 in icon mode. Note: If internally generated VLCD must not be lower than VDD. Note: V DD 4V
When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. Table 11 Use of the VA and VB registers MODE VA VB VLCD icon mode
Normal operation VLCD character mode
1997 Apr 04
29
Philips Semiconductors
Product specification
LCD controller/driver
11 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS, and R/W are required. See Chapter 7. In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. Note that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figs 14 to 17 for examples of bus protocol. In 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. 12 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 12.1 Characteristics of the I2C-bus
PCF2113x
The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 12.2 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2113x read and write cycles is shown in Figs 23 and 24. The slow down feature of the I2C-bus protocol (receiver holds SCL low during internal operations) is not used in the PCF2113x. 12.3 Definitions
* Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
1997 Apr 04
30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.18 System configuration.
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.19 Bit transfer.
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.20 Definition of START and STOP conditions.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBC602
1
2
8
9
clock pulse for acknowledgement
Fig.21 Acknowledgement on the I2C-bus.
1997 Apr 04
31
ook, full pagewidth
1997 Apr 04
acknowledgement from PCF2113x S
Philips Semiconductors
LCD controller/driver
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
MGG002
32
S 011101A0 0 PCF2113x slave address R/W
Product specification
PCF2113x
Fig.22 Master transmits to slave receiver; write mode.
agewidth
1997 Apr 04
acknowledgement S
Philips Semiconductors
LCD controller/driver
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n
0 bytes Co
1 byte
n 0 bytes
acknowledgement
acknowledgement
no acknowledgement
33
S
SLAVE ADDRESS (1) Last data byte is a dummy byte (may be omitted).
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGG003
Product specification
PCF2113x
Fig.23 Master reads after setting word address; write word address, set RS; `read data'.
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth
acknowledgement from PCF2113x
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGG004
Fig.24 Master reads slave immediately after first byte; read mode (RS previously defined).
book, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.25 I2C-bus timing diagram.
1997 Apr 04
34
Philips Semiconductors
Product specification
LCD controller/driver
13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI VO II IO IDD, ISS, ILCD Ptot PO Tstg supply voltage LCD supply voltage input voltage OSC, RS, R/W, E and DB7 to DB0 output voltage R1 to R18, C1 to C60 and VLCD DC input current DC output current VDD, VSS or VLCD current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 -10 -10 -50 - - -65
PCF2113x
MAX. +6.5 +7.5 VDD + 0.5 VLCD + 0.5 +10 +10 +50 400 100 +150 V V V V
UNIT
mA mA mA mW mW C
14 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
1997 Apr 04
35
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
15 DC CHARACTERISTICS VDD = 1.8 to 4.0 V (external VLCD: VDD = 1.8 to 5.5 V); VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VDD VLCD ISS ISS1 ISS3 ISS4 ISS5 supply voltage supply voltage LCD supply voltage supply current, external VLCD supply current 1 supply current 3 supply current 4 (icon mode) supply current 5 (power-down mode) supply current, internal VLCD supply current 6 supply current 8 supply current 9 (icon mode) Power-on reset voltage level VDD = 3 V; VLCD = 5 V; note 2 VDD = 3 V; VLCD = 2.5 V; note 2 note 4 VDD = 3 V; VLCD = 5 V; note 2 VDD = 3 V; VLCD = 2.5 V; note 2 VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS, R/W = 1; OSC = 0; PD = 1 notes 1, 3 - - - - 200 200 100 1.3 - - - - - 4 - 0.15 - 400 400 - 1.6 A A A V note 1 - - - - 60 45 25 0.5 120 80 45 5 A A A A internal VLCD generation external VLCD 1.8 1.8 2.2 - - - 4.0 5.5 6.5 V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ISS ISS6 ISS8 ISS9 VPOR Logic VIL1 VIH1 VIL(PD) VIH(PD) VIL(osc) VIH(osc) IOL(DB) IOH(DB) Ipu IL1
LOW level input voltage T1, E, RS, R/W, DB[7..0] and SA0 HIGH level input voltage T1, E, RS, R/W, DB[7..0] and SA0 LOW level input voltage PD HIGH level input voltage PD LOW level input voltage OSC HIGH input voltage OSC LOW level output current DB[7..0] HIGH level output current DB[7..0] pull-up current DB[7..0] leakage current OSC, E, RS, R/W, DB[7..0] and SA0 VOL = 0.4 V; VDD = 5 V VOH = 4 V; VDD = 5 V VI = VSS VI = VDD or VSS
0 0.7VDD 0 0.8VDD 0 1.6 -1.0 0.04 -1.0
0.3VDD VDD 0.2VDD VDD VDD - - 1 +1.0
V V V V V mA mA A A
VDD - 1.5 V
VDD - 0.1 -
1997 Apr 04
36
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
SYMBOL I2C-bus SDA AND SCL VIL2 VIH2 IL2 Ci IOL(SDA) RROW RCOL Vtol1 Vtol2a Vtol2b Vtol2c TC0 TC1 TC2 TC3 Notes
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOW level input voltage HIGH level input voltage input leakage current input capacitance LOW level output current (SDA) VI = VDD or VSS note 5 VOL = 0.4 V; VDD = 5 V note 6 note 7 Tamb = 25 C;VLCD < 3 V; note 3 Tamb = 25 C; VLCD < 4 V; note 3 Tamb = 25 C; VLCD < 5 V; note 3 note 8 note 8 note 8 note 8
0 0.7VDD -1 - 3 - - - - - - - - - -
- - - - -
0.3VDD 5.5 +1 10 -
V V A pF mA
LCD outputs row output resistance R1 to R18 bias voltage tolerance R1 to R18 and C1 to C60 VLCD tolerance VLCD tolerance VLCD tolerance VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 10 15 20 - - - -7.6 -8.4 -10.4 -12.4 30 40 130 200 350 400 - - - - k k mV mV mV mV mV/K mV/K mV/K mV/K column output resistance C1 to C60 note 6
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive. 2. Tamb = 25 C; fOSC = 200 kHz. 3. LCD outputs are open-circuit; HV generator is on; load current IVLCD (at VLCD) = 5 A. 4. Resets all logic when VDD < VPOR; 3 OSC clock cycles required. 5. Tested on sample basis. 6. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 A; outputs measured one at a time; external VLCD. 7. LCD outputs open-circuit; external VLCD. 8. Temperature coefficient at VOP = 5.0 V. Typical range 2 mV/K.
1997 Apr 04
37
Philips Semiconductors
Product specification
LCD controller/driver
16 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 - 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL fFR fOSC fOSC tOSCST PARAMETER LCD frame frequency (internal clock) oscillator frequency (not available at any pin) external clock frequency oscillator start-up time after power-down CONDITIONS VDD = 5.0 V MIN. 45 140 140 - TYP. 81 250 - 200
PCF2113x
MAX. 147 450 450 300
UNIT Hz kHz kHz s
Bus timing characteristics: parallel interface; note 1 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X) Tcy PWEH tASU tAHD tDSW tHD Tcy PWEH tASU tAH tDHD tHD enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER) enable cycle time enable pulse width address set-up time address hold time data delay time data hold time 500 220 50 25 - 20 - 1.3 0.6 100 0 - - - 0.6 0.6 0.6 - ns ns ns ns ns ns
Timing characteristics: I2C-bus interface; note 1 fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf CB tSU;STA tHD;STA tSU;STO tSW Note 1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency SCL clock low period SCL clock high period data set-up time data hold time SCL, SDA rise time SCL, SDA fall time capacitive bus line load set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus 400 - - - - 300 300 400 - - - 50 kHz s s ns ns ns ns pF s s s ns
1997 Apr 04
38
Philips Semiconductors
Product specification
LCD controller/driver
17 TIMING CHARACTERISTICS
PCF2113x
ndbook, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH
R/W
V IL1 PW EH
VIL1 t AH VIL1 tH VIH1 VIL1
MLA798 - 1
E
VIH1 VIL1
VIH1 VIL1 t DSW VIH1 Valid Data VIL1 Tcy
DB0 to DB7
Fig.26 Parallel bus write operation sequence; writing data from microcontroller to PCF2113x.
ndbook, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH VIH1
R/W
VIH1
PW EH E VIL1 VIH1 VIH1
t AH VIL1 VIL1
t DDR DB0 to DB7 VOH1 VOL1 Tcy
t DHR VOH1 VOL1
MLA799 - 1
Fig.27 Parallel bus read operation sequence; reading data from PCF2113x to microcontroller.
1997 Apr 04
39
Philips Semiconductors
Product specification
LCD controller/driver
18 APPLICATION INFORMATION
PCF2113x
handbook, full pagewidth
P20 P21 P80CL51 P22
RS R/W E
R17, R18
2
R1 to R16 PCF2113x 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGG005
P17 to P10
8
DB7 to DB0
C1 to C60
Fig.28 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, full pagewidth
P10 P11 P80CL51 P12
RS R/W E
R17, R18
2
R1 to R16 PCF2113x 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGG006
P17 to P14
4
DB7 to DB4
C1 to C60
Fig.29 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
OSC VDD
R17, R18
2
VDD R1 to R16 PCF2113x 100 nF VLCD 100 nF VSS C1 to C60 16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
VSS
8 DB7 to DB0 E RS R/W
MGG007
Fig.30 Typical application using parallel interface.
1997 Apr 04
40
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
handbook, full pagewidth
VDD VDD
VDD
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2113x 16
100 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C60
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
VSS
OSC VDD
DB3/SAO
R17, R18
2
VDD R1 to R16 PCF2113x 16
100 nF VSS
VLCD 100 nF VSS SCL SDA C1 to C60
1 x 24 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
SCL SDA
MASTER TRANSMITTER PCF84C81A; P80CL410
MGG008
Fig.31 Application using I2C-bus interface.
1997 Apr 04
41
Philips Semiconductors
Product specification
LCD controller/driver
18.1 8-bit operation, 1-line display using internal reset
PCF2113x
However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 12 step 3). Thus, DB4 to DB7 of the `function set' are written twice. 18.3 8-bit operation, 2-line display
Table 13 shows an example of a 1-line display in 8-bit operation. The PCF2113x functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and DDRAM contents remain unchanged, display data entered first can be displayed when the `return home' operation is performed. 18.2 4-bit operation, 1-line display using internal reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 5). Note that both lines of the display are always shifted together; data does not shift from one line to the other. 18.4 I2C operation, 1-line display
The program must set functions prior to 4-bit operation. Table 12 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2113x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required.
A control byte is required with most instructions (see Table 16).
Table 12 4-bit operation, 1-line display example; using internal reset STEP 1 2 INSTRUCTION power supply on (PCF2113x is initialized by the internal reset circuit) function set RS 0 3 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed _ turns on display and cursor; entire display is blank after initialization DISPLAY OPERATION initialized; no display appears
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display on/off control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 _
5
entry mode set 0 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
`write data' to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0 P_
1997 Apr 04
42
1997 Apr 04 43
Philips Semiconductors
Table 13 8-bit operation, 1-line display example; using internal reset (character set `A')
LCD controller/driver
STEP 1 2
INSTRUCTION power supply on (PCF2113x is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right writes `H' | |
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
6 7 to 11
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_
12 13 14 15 16
`write data' to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS_ PHILIPS_ HILIPS _ ILIPS | | | M_ writes `S' sets mode for display shift at the time of write writes space Product specification writes `M' entry mode set `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM
PCF2113x
1997 Apr 04 44
Philips Semiconductors
STEP 17 18 19 20 21 22 23 24 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1
INSTRUCTION `write data' to CGRAM/DDRAM 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 0 1
DISPLAY MICROKO MICROKO MICROKO ICROCO MICROCO MICROCO_ ICROCOM_ | | | writes `O'
OPERATION
LCD controller/driver
cursor/display shift shifts only the cursor position to the left shifts only the cursor position to the left writes `C' correction; the display moves to the left shifts the display and cursor to the right shifts only the cursor to the right writes `M' cursor/display shift `write data' to CGRAM/DDRAM cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM
25
return home 0 0 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position (address 0)
Product specification
PCF2113x
1997 Apr 04 45
Philips Semiconductors
Table 14 8-bit operation, 1-line display and icon example; using internal reset (character set `A')
LCD controller/driver
STEP 1 2
INSTRUCTION power supply on (PCF2113x is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display and VLCD = V0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted sets the CGRAM address to position of character 0; the CGRAM is selected writes data to CGRAM for icon even phase; icons appears | |
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
set CGRAM address 0 0 0 1 0 0 0 0 0 0 _
6 7
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
8
set CGRAM address 0 0 0 1 1 1 0 0 0 0 _ sets the CGRAM address to position of character 4; the CGRAM is selected writes data to CGRAM for icon odd phase | | function set
9 10
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
11 12 13
Product specification
PCF2113x
0 0 0
0 0 0
0 0 0
0 0 0
1 0 1
1 0 1
0 1 0
0 0 0
0 1 0
1 0 1
_ _ _
sets H = 1 icons blink sets H = 0
icon control function set
1997 Apr 04 46
Philips Semiconductors
STEP 14 set DDRAM address 0 15 0 1 0
INSTRUCTION 0 0 0 0 0 0
DISPLAY
OPERATION sets the DDRAM address to the first position; DDRAM is selected
LCD controller/driver
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_ writes `P'; the cursor is incremented by 1 and shifted to the right writes `H' | | return home 0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position (address 0)
16 17 to 20
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_
21
Product specification
PCF2113x
1997 Apr 04 47
Philips Semiconductors
Table 15 8-bit operation, 2-line display example; using internal reset
LCD controller/driver
STEP 1 2
INSTRUCTION power supply on (PCF2113x is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 0 0 _ 0 0 0 0 0 0 1 1 1 0 _ 0 0 0 0 0 0 0 1 1 0
DISPLAY
OPERATION initialized; no display appears sets to 8-bit operation; selects 2-line display and voltage generator off
3
display on/off control
turns on display and cursor; entire display is blank after initialization
4
entry mode set
sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right | | |
5
`write data' to CGRAM/DDRAM P_ 1 0 0 1 0 1 0 0 0 0
6 to 10
11
`write data' to CGRAM/DDRAM PHILIPS_ 1 0 0 1 0 1 0 0 1 1 PHILIPS 0 0 1 1 0 0 0 0 0 0 _
writes `S'
12
set DDRAM address
sets DDRAM address to position the cursor at the head of the 2nd line
13
`write data' to CGRAM/ DDRAM PHILIPS 1 0 0 1 0 0 1 1 0 1 M_ | | |
writes `M' Product specification
PCF2113x
14 to 19
1997 Apr 04 48
Philips Semiconductors
STEP 20
INSTRUCTION `write data' to CGRAM/DDRAM
DISPLAY writes `O' PHILIPS
OPERATION
LCD controller/driver
1 21
0
0
1
0
0
1
1
1
1
MICROCO_ sets mode for display shift at the time of write PHILIPS
`write data' to CGRAM/DDRAM 0 0 0 0 0 0 0 1 1 1 MICROCO_ HILIPS 1 0 0 1 0 0 1 1 0 1 ICROCOM_ | | |
22
`write data' to CGRAM/DDRAM
writes `M'; display is shifted to the left; the first and second lines shift together
23
24
return home PHILIPS 0 0 0 0 0 0 0 0 1 0 MICROCOM
returns both display and cursor to the original position (address 0)
Product specification
PCF2113x
1997 Apr 04 49
Philips Semiconductors
Table 16 Example of I2C operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) STEP 1 2 I2C start I2C BYTE slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 Co 0 4 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction _ 1 1 1 0 1 _ 0 0 1 1 0 1 _ for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed 8 slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 9 Co 0 10 1 RS 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 _ Ack 1 send a control byte for `write data' _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets) send a control byte for `function set' control byte sets RS for following data bytes during the acknowledge cycle SDA will be pulled-down by the PCF2113x DISPLAY OPERATION initialized; no display appears
LCD controller/driver
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1
5
display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0
7
I2C start
Product specification
`write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 P_ writes `P'; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right
PCF2113x
1997 Apr 04 50
Philips Semiconductors
STEP 11 `write data' to DDRAM
I2C BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1
DISPLAY writes `H' PH_ | | | |
OPERATION
LCD controller/driver
12 to 15
16
`write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 1 1 1 PHILIPS_ PHILIPS_ writes `S'
17 18
(optional I2C stop) I2C start + slave address for write (as step 8) control byte Co 1 RS 0 0 0 0 0 0 0 0 0 0 0 0 0 Ack 1
PHILIPS_ sets DDRAM address 0 in Address Counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR)
19
return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C interface to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed; therefore the content of the DR was unknown. The R/W has to be set to 1 while still in I2C-write mode. DDRAM content will be read from following instructions Product specification
20 21
I2C start slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
PHILIPS
22
control byte for read Co 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS
PCF2113x
1997 Apr 04 51
Philips Semiconductors
STEP 23
I2C BYTE `read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0
DISPLAY
OPERATION 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C interface 8 x SCL; code of letter `H' is read first; during master acknowledge code of `I' is loaded into the I2C interface no master acknowledge; after the content of the I2C interface register is shifted out no internal action is performed; no new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted
LCD controller/driver
PHILIPS
24
`read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS
25
`read data': 8 x SCL + no master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1 PHILIPS
26 Notes
I2C stop
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
Product specification
PCF2113x
1997 Apr 04 52
Philips Semiconductors
Table 17 Initialization by instruction, 8-bit interface (note 1)
LCD controller/driver
STEP power-on or unknown state | wait 2 ms after VDD rises above VPOR | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait 2 ms | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait more than 40 s | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | | RS 0 0 0 0 R/W 0 0 0 0 DB7 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 | Initialization ends DB4 1 0 0 0 DB3 0 1 0 0 DB2 M 0 0 1 DB1 0 0 0 I/D DB0 H 0 1 S display off clear display entry mode set DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X DB4 1 DB3 X DB2 X DB1 X DB0 X
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (interface is 8 bits long); specify the number of display lines.
Product specification
Note 1. X = don't care.
PCF2113x
1997 Apr 04 53
Philips Semiconductors
Table 18 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
LCD controller/driver
STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 Wait 2 ms | RS 0 Wait 40 s | RS 0 R/W 0 DB7 0 | RS 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 DB7 0 0 0 0 1 0 0 0 0 | Initialization ends DB6 0 0 M 0 0 0 0 0 1 DB5 1 1 0 0 0 0 0 0 I/D DB4 0 0 H 0 0 0 1 0 S entry mode set display off clear display DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) function set (set interface to 4 bits long) interface is 8 bits long function set (interface is 4 bits long) specify number of display lines
Product specification
PCF2113x
Philips Semiconductors
Product specification
LCD controller/driver
19 BONDING PAD LOCATIONS
PCF2113x
y
C29
C30 C31 C32 C33 C34 C35
C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49
handbook, full pagewidth
C50 C51 C52 C53
4.08 C15 mm
C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 Y X SCL
C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16
0 0
C54 C55 C56 C57 C58 C59 C60 R18 R16 R15 R14 R13 R12 R11 R10 R9 VLCD1 VLCD2 VSS2
x
PCF2113x
VSS1 T1 PD OSC VDD1
SDA
R/W
C1 R8 R7
R6 R5
R4 R3 R2 R1
R17
E
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
3.94 mm
MGG009
Fig.32 Bonding pad locations.
1997 Apr 04
54
DB0 VDD2
Philips Semiconductors
Product specification
LCD controller/driver
Table 19 Bonding pad locations (dimensions in m) All x/y coordinates are referenced to centre of chip (see Fig.32). SYMBOL VDD1 OSC PD T1 VSS1 VSS2 VLCD2 VLCD1 R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 1997 Apr 04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PAD X 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1811.3 1536.5 1416.5 1296.5 1176.5 983.9 863.9 743.9 623.9 503.9 383.9 263.9 143.9 23.9 -96.1 Y -1547.1 -1416.5 -1285.9 -1155.3 -1024.7 -822.1 -633.9 -446.3 -264.0 -144.0 -24.0 96.0 216.0 336.0 456.0 576.0 696.0 889.4 1009.4 1129.4 1249.4 1369.4 1489.4 1609.4 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7L 55 SYMBOL C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 PAD X -216.1 -336.1 -456.1 -576.1 -696.1 -816.1 -936.1 -1056.1 -1176.1 -1296.1 -1488.7 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3 -1811.3
PCF2113x
Y 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1877.7 1609.4 1489.4 1369.4 1249.4 1129.4 1009.4 889.4 769.4 649.4 529.4 409.4 289.4 169.4 23.2 -96.8 -216.8 -336.8 -456.8 -649.4 -769.4 -889.4 -1009.4 -1129.4 -1249.4 -1369.4 -1489.4 -1609.4
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
SYMBOL C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA E RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD2 Sign C1 Sign C2 Sign f 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
PAD
X -1542.7 -1422.4 -1302.4 -1182.4 -1062.4 -942.4 -822.4 -702.4 -582.4 -462.4 -271.2 -130.2 74.4 205.1 335.7 468.8 603.8 738.8 873.8 1008.8 1143.8 1278.8 1413.8 1546.0 -1518.0 1405.0 -1491.0
Y -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1877.7 -1387.7 1671.3 1602.3
1997 Apr 04
56
Philips Semiconductors
Product specification
LCD controller/driver
20 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
PCF2113x
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
ISSUE DATE 95-12-19 97-08-04
1997 Apr 04
57
Philips Semiconductors
Product specification
LCD controller/driver
21 SOLDERING 21.1 Introduction
PCF2113x
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 21.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 21.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1997 Apr 04
58
Philips Semiconductors
Product specification
LCD controller/driver
22 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2113x
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 23 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 04
59
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/00/02/pp60
Date of release: 1997 Apr 04
Document order number:
9397 750 01753

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